1. Field of the Invention
The present invention relates to a rate dematching processor which performs rate dematching at a receiving end with respect to the data that has been subjected to rate matching at a sending end, that is, the rate dematching processor which inserts, at a receiving end, dummy data into a position of the data that has been thinned out at the sending (transmitting) end or deletes, at the receiving end, the repeated data at the sending end.
2. Description of the Related Art
As one of 3rd Generation Partnership Project (3GPP) international standards relating to a mobile radio (wireless) communication system, a wideband code division multiple access (W-CDMA) system has been known. This system involves various processes. A rate matching process is one of the processes, which adjusts differences in rate between send data and a physical channel.
In the rate matching process, when a rate of send data is higher than a rate of the physical channel, several pieces of data are thinned out (hereinafter, referred to as “punctured”) in a sending data string, thereby allowing the rate of send data to correspond to the rate of the physical channel. On the other hand, when the rate of send data is lower than the rate of physical channel, several pieces of data are repeated in the sending data string, thereby allowing the rate of send data to correspond to the rate of the physical channel.
At receiving end, a rate dematching process, which is a reverse process of the rate matching process, is performed. In the rate dematching process, dummy data are inserted into a position of the data that has been punctured at sending end, or the data repeated in sending end is deleted.
The apparatus that performs the above rate dematching process has been disclosed in JP-A-2002-199048 (Japanese Patent Application Publication No. 2002-199048). The apparatus disclosed in JP-A-2002-199048 (hereinafter, referred to as “conventional apparatus”) comprises, as shown in FIG. 1, information bit memory (memory for information bit) 202, first parity bit memory (memory for first parity bit) 203, second parity bit memory (memory for second parity bit) 204, switch 201 which sorts input data into these three memories 202 to 204, first parity bit rate dematching circuit (rate dematching circuit for first parity bit) 205 which applies the rate dematching process to a first parity bit, and second parity bit rate dematching circuit (rate dematching circuit for second parity bit) 206 which applies the rate dematching process to a second parity bit. This conventional apparatus performs rate dematching process to the data that have been punctured at sending end to the turbo-encoded data with coded rate 1/3. Note that the data that have been turbo-encoded are made up of three-bit strings; an information bit, a first parity bit and a second parity bit.
Next, an operation of the conventional apparatus will be described. Input data are sorted and the sorted data are stored in any of the information bit memory 202, the first parity bit memory 203 and the second parity bit memory 204. The switch 201 sorts the input data into these three memories 202 to 204. That is, when an information bit is input, the switch 201 sorts it into the information bit memory 202. Likewise, when a first parity bit is input, the switch 201 sorts it into the first parity bit memory 203. When a second parity bit is input, the switch 201 sorts it into the second parity bit memory 204.
The data stored in the information bit memory 202 are output, as device output A, to outside of the apparatus without change. The data stored in the first parity bit memory 203 are input to the first parity bit rate dematching circuit 205. The first parity bit rate dematching circuit 205 performs rate dematching process to the input data and outputs the processed data to outside of the apparatus as device output B. The data stored in the second parity bit memory 204 are input to the second parity bit rate dematching circuit 206. The second parity bit rate dematching circuit 206 performs rate dematching process to the input data and outputs the processed data to outside of the apparatus as device output C.
In 3GPP, a new function called “High Speed Downlink Packet Access (HSDPA)” will be added to W-CDMA international standard for the purpose of realizing much faster mobile radio communication. HSDPA is a technique for speeding up a downward packet transmission (that is, transmission from a base station to a mobile station). As one of the process in the HSDPA, rate-matching process called “first rate matching” has been known. The following limitations has been set in first rate matching process, as compared to the general rate matching process:
(1) Repeating is not performed (that is, only puncturing is performed).
(2) Total data amount of information bit, first parity bit and second parity bit after first rate matching is limited by constant value M.
With respect to the limitation (2), in the case where the total data amount M after first rate matching process is, for example, 30 bits, the following cases are possible. The following cases do not cover every cases, but shows typical cases.
(Case 1)
In the case of 20 bits for information bit, 20 bits for first parity bit and 20 bits for second parity bit in a state before first rate matching process, first parity bit and second parity bit are punctured by 15 bits, respectively, resulting in 30 bits in total. That is, in a state after first rate matching process, the information bit, first parity bit and second parity bit have 20 bits, 5 bits and 5 bits, respectively.
(Case 2)
In the case of 30 bits for information bit, 30 bits for first parity bit and 30 bits for second parity bit in a state before first rate matching process, first parity bit and second parity bit are punctured by 30 bits, respectively, resulting in 30 bits in total. That is, in a state after first rate matching process, the information bit, first parity bit and second parity bit have 30 bits, 0 bits and 0 bits, respectively.
(Case 3)
In the case of 10 bits for information bit, 10 bits for first parity bit and 10 bits for second parity bit in a state before first rate matching, any of these bits are not punctured, resulting in 30 bits in total. That is, in a state after first rate matching process, the information bit, first parity bit and second parity bit have 10 bits, 10 bits and 10 bits, respectively.
In the above three cases, the maximum data amount for each of the information bit, first parity bit and second parity bit after first rate matching process can be assumed as follows; 30 bits for information bit (case 2), 10 bits for first parity bit (case 3), and 10 bits for second parity bits (case 3). In this case, when first rate dematching process, which is a reverse process of first rate matching process, is performed in the conventional apparatus, capacities of 30 bits, 10 bits and 10 bits are required for the memories 202, 203 and 204 of FIG. 1, respectively. It follows that total capacity N of the memories 202, 203, and 204 is 50 bits, which is larger than the total data amount M (30 bits) after first rate matching process by 20 bits.
Since the values M and N are small in the above example, the difference between the value M and the value N is correspondingly small (20 bits). However, the value of M actually used in practical operations is considerably large (thousands to tens of thousands). Accordingly, the difference between M and N is considerably large.